Method and system for clock skew reduction in clock trees

ABSTRACT

A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.

FIELD OF THE INVENTION

The present invention relates to methods and systems for reducing clockskew, especially after the production of an integrated circuit iscompleted.

BACKGROUND OF THE INVENTION

Most integrated circuits include many synchronized components. Thesesynchronized components can include logic gates, inverters, flip-flops,memory cells and the like. Synchronized components are triggered by aclock signal. The clock signals are distributed among the synchronizedcomponents using clock distribution networks (also referred to as clocktrees).

A typical clock tree includes multiple clock tree branches and multipleclock tree taps. Each clock tree branch splits to multiple clock treetaps. Clock signals propagate along a common clock path and thenpropagate along non-common clock paths. The non-common clock paths caninclude passive and optionally active components that can have differentcharacteristics. These components can introduce clock skews. Clock skewscan cause timing violations such as setup violations and/or holdviolations.

There are multiple prior art methods and systems for reducing clockskews and for measuring clock skews. Some clock skew reduction methodsare implemented during the design stages of the integrated circuit whileother techniques can be implemented after production. A first methodinvolved optimizing the topology of the clock tree. This method caninclude designing balanced clock trees and the like. Another clock skewreduction method involves clock reversing. Yet another clock skewreduction method included introducing delays in a large number of clocktree branches. The following articles, patents and patent applicationsillustrate various clock skew reduction methods and systems: “Reduceddelay uncertainty in high performance clock distribution networks”, D.Velenis, M. C. Papaefthymiou, E. G. Friedman, Proceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE '03)1530-1591/03; “Clock generation and distribution for the 130-nm Itanium®processor with 6-MB on-die L3 cache”, S. Tam, R. D. Limaye, U. N. Desai,IEEE journal on solid-state circuits, vol. 39, no. 4, April 2004; U.S.patent application publication Ser. No. 2004/0128634 of Johnson et al.;U.S. patent application publication Ser. No. 2005/0107970 of Franch etal.; U.S. patent application publication Ser. No. 2005/0102643 of Hou,et al.; U.S. patent application publication Ser. No. 2003/0101423 ofThorp, et al.; U.S. patent application publication Ser. No. 2004/0181705of Gauthier, et al.; U.S. patent application publication Ser. No.2002/0196067 of Schultz; U.S. Pat. No. 6,957,357 of Liu; U.S. Pat. No.6,943,610 of Saint-Laurent; U.S. Pat. No. 6,941,532 of Haritsa et al.and U.S. Pat. No. 6,741,122 of Kapoo.

There is a need to provide efficient systems and methods for reducingclock skew.

SUMMARY OF THE PRESENT INVENTION

A system and a method for clock skew reduction, as described in theaccompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 is a schematic diagram of a system, according to an embodiment ofthe invention;

FIG. 2 is a schematic diagram of a system, according to an embodiment ofthe invention;

FIG. 3 is a schematic diagram of a portion of a clock tree, according toan embodiment of the invention;

FIG. 4 is a schematic diagram of a multiple fuses, a selection circuitand multiple variable delay components, according to an embodiment ofthe invention;

FIG. 5 is a schematic diagram of a portion of a system, according to anembodiment of the invention;

FIG. 6 is a schematic diagram of various synchronized components andpaths, according to an embodiment of the invention; and

FIG. 7 is a flow chart of a method for reducing clock skew, according toan embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

According to an embodiment of the invention a system and method forreducing clock skews after production are provided.

According to an embodiment of the invention a system having clock skewreduction capabilities is provided. The system includes a clock tree,multiple variable delay components, a first set of fuses indicative ofidentities of variable delay components that belong to a first set ofvariable delay components, a second set of fuses indicative of delayvalues of the variable delay components that belong to the first set ofvariable delay components, and a second set of variable delay componentsthat are set to at least one default delay value.

The first set of variable delay components can be selected in view ofvarious timing related tests of the device, and especially ofoperational paths that include components that receive different clocksignals from different edges of the clock tree. The system can includetest paths that facilitate a determination of timing margins associatedwith operational paths. These timing margins as well as timingdifferences between different clock signals define which variable delaycomponents belong to the first set of variable delay components.

Conveniently, the number of fuses required to allow an integratedcircuit to operate properly is relatively limited, especially inrelation to an amount of fuses that should be required to set each andevery variable delay unit.

According to an embodiment of the invention a method for reducing clockskews is provided. The method includes: (i) providing a clock tree thatincludes a set of variable delay components, (ii) selecting a first setof variable delay components in view of timing violations occurring dueclock skews, (iii) setting delay values of variable delay componentsthat form a first set of variable delay components by programming fuses,and (iv) setting delay values of variable delay components that form asecond set of variable delay components to at least one default value.

According to an embodiment of the invention a method for reducing clockskews is provided. The method includes: (i) providing a clock tree thatcomprises a set of variable delay components; (ii) setting delay valuesof variable delay components that form a first set of variable delaycomponents by programming fuses; (iii) and (iv) setting delay values ofvariable delay components that form a second set of variable delaycomponents to at least one default value. Conveniently, whereas thefirst set is smaller than one half of the second set.

FIG. 1 illustrates a system 200, according to an embodiment of theinvention. System 200 can include one or more integrated circuits, caninclude one or more voltage supply units, can be a mobile system such asbut not limited to a cellular phone, a laptop computer, a personal dataaccessory and the like.

System 200 includes a clock tree 210, a first set of fuses 230, a secondset of fuses 235, a selection circuit 250, a first set of variable delaycomponents 240, a second set variable delay components 245 and multiplesynchronized component groups 281-282 and 284.

The clock tree 210 includes multiple variable delay components 240 and245. Conveniently, the number of variable delay components is very largeand can conveniently exceed few hundreds. The number of variable delaycomponents can also exceed one thousand.

The inventors found that even if a system includes a large number ofvariable delay components then only few variable delay components shouldbe adjusted in order to provide a functional system. The system istested in order to select which variable delay components should be setto a delay value other then their default delay value. These delayvalues can be determined by programming fuses.

By setting only a small portion of the multiple variable delaycomponents, the number of fuses can be relatively small. In addition,the delay value of the selected variable delay components can be definedwith relatively high resolution, as many fuses can be allocated per eachselected variable delay component.

For example, assuming that there are three hundred 4-bit variable delaycomponents. If each delay unit is set by four fuses then one thousandand two hundred fuses were required. If, for example, only tenadjustable delay components are selected and set to a value that differsfrom their default value then ninety fuses are required to identify eachof these ten selected variable delay units (nine fuses per selectedvariable delay unit), and forty additional bits are required for settingthe ten delay values of the ten selected variable delay components.

Referring to FIG. 1, The selection circuit 250 is connected to the firstset of fuses 230, to the second set of fuses 235 and to each of thevariable delay components within the clock tree 210. For simplicity ofexplanation the selection circuit 210 is illustrated as being connectedto two variable delay components that form a first set of variable delaycomponents 240. It is noted that the number of variable delay componentsthat form the first set of variable delay components can exceed (andeven well exceed) two.

According to an embodiment of the invention, most of the variable delaycomponents are set to provide a default delay value. Conveniently, thefirst set of variable delay components 240 is smaller than half of thesecond set of variable delay components 245. Conveniently, the first setof variable delay components 240 is smaller than one sixth of the secondset of variable delay components 245. The inventors used a 1:29 ratiobetween these two sets.

The clock tree 210 provides a first clock signal to synchronizedcomponents group 281. The clock tree 210 provides another clock signalto synchronized components group 282. The clock tree 210 provides afurther clock signal to synchronized components group 284. Each one ofthe synchronized components groups 281, 282 and 284 can include one ormore latches, transistors, flip-flops, and the like.

Synchronized components groups 281, 282 and 284 are connected to eachother and define multiple operational paths. The functionality of theoperational paths can be hampered due to clock skews. By adjusting somevariable delay components within clock tree 210 these clock skews can bereduced.

Conveniently, the first set of fuses 230 are indicative of theidentities of variable delay components that belong to the first set ofvariable delay components 240. The second set of fuses 235 areindicative of the delay values of the variable delay components thatbelong to the first set of variable delay components.

The selection circuit 250 sends to each variable delay component thatbelongs to the first set of variable delay components 240 a delay valuethat determines the delay of that variable delay component.

Conveniently, the second set of variable delay components 245 are set toat least one default delay value.

FIG. 2 is a schematic diagram of system 200′, according to an embodimentof the invention.

System 200′ of FIG. 2 resembles system 200 of FIG. 1 but differs by theselection of variable delay components. In other words, system 200 wastested and certain variable delay components were selected to be set toa delay value that differs from their corresponding default delayvalues. System 200′ was tested and other delay components were selected.

FIG. 3 is a schematic diagram of a portion 211 of clock tree 210,according to an embodiment of the invention.

Those of skill in the art will appreciate that the invention can beapplied to clock tree portions that have different structures, as wellas to clock tree portions that include other components (such asbuffers, repeaters, drivers) as well as to clock trees that includefewer components.

Portion 211 is connected, either directly or indirectly, to a clocksignal generator (not shown). At the root of portion 211 the clocksignal is split to two clock paths and is provided to two clock dividers11 and 11′. The first clock divider 11 is connected to two variabledelay components VDC1 12 and VDC2 13.

VCD1 12 is connected, via connector C1 21, to first logic gate G1 24.The output of G1 24 is connected to one end of conductor C11 31. Theother end of conductor C11 31 is connected to three different clock treetaps. One clock tree tap includes conductor C16 36. Another clock treetap includes conductors C14 34 and C15 35. A further clock tree tapincludes conductors C14 34, C13 33 and C12 32. Conductor C12 32 ends atclock tree edge 271. Conductor C15 35 ends at clock tree edge 272.Conductor C16 36 ends at clock tree edge 273.

VCD2 13 is connected, via connector C2 22, to second logic gate G2 25.The output of G2 25 is connected to one end of conductor C21 41. Theother end of conductor C21 41 is connected to three different clock treetaps. One clock tree tap includes conductor C26 46. Another clock treetap includes conductors C24 44 and C25 45. A further clock tree tapincludes conductors C24 44, C23 43 and C22 42. Conductor C22 42 ends atclock tree edge 274. Conductor C25 45 ends at clock tree edge 275.Conductor C26 46 ends at clock tree edge 276.

The second clock divider 11′ is connected to variable delay componentVDC3 14. VCD3 14 is connected, via connector C3 23, to the third logicgate G3 26. The output of G3 26 is connected to one end of conductor C3151. The other end of conductor C31 51 is connected to three differentclock tree taps. One clock tree tap includes conductor C36 56. Anotherclock tree tap includes conductors C34 54 and C35 55. A further clocktree tap includes conductors C34 54, C33 53 and C32 52. Conductor C32 52ends at clock tree edge 277. Conductor C35 55 ends at clock tree edge278. Conductor C36 56 ends at clock tree edge 279.

These different conductors (and gates) define multiple clock paths.These clock paths can be viewed as belonging to three different clockpath groups, one group per variable delay component. A first group ofclock paths includes three clock paths that are defined between variabledelay component VDC1 21 and clock tree edges 271, 272 and 273. A secondgroup of clock paths includes three clock paths that are defined betweenvariable delay component VDC2 23 and clock tree edges 274, 275 and 276.A third group of clock paths includes three clock paths that are definedbetween variable delay component VDC3 14 and clock tree edges 277, 278and 279. The variable delay components can compensate for clock skewsbetween the various groups of clock paths.

Conveniently, these different paths can cause a non-negligiblenon-common clock skews. In other words, the variable delay componentsare located at locations that define long non-common paths with theedges 271-279 of clock tree 210.

Conveniently, the clock tree portion 211 is designed such that its tapsare short (introduce only short insertion delay, if any). Thus, thevariable delay components can be placed before the clock tree taps.

FIG. 4 is a schematic diagram of a multiple fuses 239(1)-230(K) and235(1)-235(K), a selection circuit 250 and multiple variable delaycomponents 240 and 245, according to an embodiment of the invention. Kis a positive integer. Index k ranges between 1 and k.

The first set of fuses 230 includes K fuse subsets 230(1)-230(K) and thesecond set of fuses 235 includes K fuse subsets 235(1)-235(K). Fusesubset 230(k) is associated with fuse subset 235(k). Fuse subset 250(k)indicates an identity of a variable delay component that is going to beset to a delay indicated by the fuse subset 235(k).

Selection circuit 250 receives K identities of selected variable delayunits ID1-IDK 311-319, as well K delay values DV1-DVK 301-309. Theselection circuit 250 can be connected to all the variable delaycomponents. It provides the delay values to the first set of variabledelay components 240 and can provide a default value to the othervariable delay components. It is noted that the default value providedby the selection circuit can determine the default delay value but thisis not necessarily so. According to an embodiment of the invention thedefault delay value of various variable delay components can by locallyset (for example by using pull-up and/or pull-down circuits), and thedefault value provided by the selection circuit does not change thelocally set default delay value. According to another embodiment of theinvention the default value can be stored by a group of fuses, but thisis not necessarily so.

FIG. 5 is a schematic diagram of a portion 209 of system 200, accordingto an embodiment of the invention.

Portion 209 include three synchronized components groups 281-284. Eachgroup can include one or more synchronized components that receivesubstantially the same clock signal. Each synchronized component groupis connected to one edge of the clock tree. Synchronized componentsgroup 281 is connected to clock tree edge 271. Synchronized componentsgroup 282 is connected to clock tree edge 272. Synchronized componentsgroup 284 is connected to clock tree edge 274.

For convenience of explanation only few components and few connectionsbetween the components are illustrated in FIG. 5. Synchronizedcomponents group 281 includes synchronized components 2811, 2812, 2813and 2814. Synchronized components group 282 includes synchronizedcomponents 2821, 2822, 2823, 2824 and 2825. Synchronized componentsgroup 284 includes synchronized components 2841, 2842, 2843, 2844, 2845and 2846.

Synchronized component 2811 is connected to synchronized component 2812.Synchronized component 2812 is also connected to synchronized components2813 and 2814. Synchronized component 2811 is connected to synchronizedcomponent 2812. Synchronized component 2813 is also connected tosynchronized components 2821 and 2845. Synchronized component 2814 isalso connected to synchronized component 2822. Synchronized component2821 is also connected to synchronized component 2822. Synchronizedcomponent 2822 is also connected to synchronized component 2823.Synchronized component 2823 is also connected to synchronized component2824. Synchronized component 2824 is also connected to synchronizedcomponents 2825, 2842 and 2844. Synchronized component 2825 is alsoconnected to synchronized component 2841. Synchronized component 2841 isalso connected to synchronized component 2842. Synchronized component2842 is also connected to synchronized component 2843. Synchronizedcomponent 2843 is also connected to synchronized component 2846.Synchronized component 2846 is also connected to synchronized component2845. Synchronized component 2845 is also connected to synchronizedcomponent 2844.

These synchronized components define multiple operational paths. Some ofthese paths include synchronized components of the same synchronizedcomponents group while other paths include synchronized components fromdifferent synchronized components groups. The latter are usuallysubjected to clock skews and timing problems.

These operational paths are tested by various tests, such as statictiming analysis, in order to determine timing problems as well as dodefine timing skews between different branches (paths) of the clocktree.

The static timing analysis can provide the timing differences betweenclock signals. These timing differences can be expressed by holdviolations. The value of hold violations was defined by monitoring pathsthat passed or failed the static timing analysis with increased holdtime positive slacks.

The inventors sorted the results of the static timing analysis accordingto the values of the positive slacks and selected the positive slack ofthe first path that passed the static timing analysis as the value ofthe hold timing violation. This value reflects the relative timingdifference that should be introduced between different clock paths.

Thus, if the timing differences between a clock path that ends at clocktree edge 271 and between another clock path that ends at clock treeedge 272 is X microseconds, then the variable delay components should beset to values that differ by this amount.

Because there are many different clock paths and many variable delaycomponents, a change in some variable delay components can cause newtiming violations. Thus, knowing the timing differences betweendifferent clock trees can still require a very large number of variabledelay component setting iterations.

According to an embodiment of the invention additional information canbe provided. This additional information indicates the timingmargins—the maximal (or substantially maximal) timing variationsintroduced by a certain variable delay component that will not introducetiming violations. These margins are also referred to as allowed timingdifferences or as negative timing slack.

FIG. 6 is a schematic diagram of various synchronized components 2811,2823 and 2846 and paths 291, 292, 291′ and 292′, according to anembodiment of the invention.

The upper portion of FIG. 6 illustrates two synchronized components suchas flip-flops 2811 and 2823, an operational path 291, a timing test path291′ and a multiplexer M1 331.

Multiplexer M1 331 selects which path out of operational path 291 andtest path 291′ is connected between flip-flops 2811 and 2823. During“normal” mode of system 200 M1 331 selects operational path 291. Duringtest mode M1 331 selects (in response to a TEST/NORMAL signal) test path291′. Signal TEST/NORMAL is provided to M1 and M2 331 and 332 by atesting component that can be long to system 200 or is connected tosystem 200.

Operational path 291 can include, for example, synchronized components2812, 2813, 2821 and 2822. Yet for another example, operational path 291can include synchronized components 2812, 2814 and 2822.

Test path 291′ is designed so that it has a shorter delay than the delayof operational path 291. The difference between these delays is alsoreferred to as delay difference. This shorter delay can assist inevaluating the amount of timing corrections that can be introducedwithout causing timing violations.

The lower portion of FIG. 6 illustrates two synchronized components suchas flip-flops 2811 and 2846, an operational path 292, a timing test path292′ and a multiplexer M2 332.

Multiplexer M2 332 selected which path out of operational path 292 andtest path 292′ is connected between flip-flops 2811 and 2846. During“normal” mode of system 200 operational path 292 is selected, whileduring test mode the test path 292′ is selected. Operational path 292can include, for example, synchronized components 2812, 2813 and 2845.Yet for another example, operational path 292 can include synchronizedcomponents 2814, 2822, 2823, 2824 and 2845.

Test path 292′ is designed so that it has a shorter delay than the delayof operational path 292. This shorter delay can assist in evaluating theamount of timing corrections that can be introduced without causingtiming violations.

It is noted that multiple test paths that have different delaydifferences. These test paths can be connected in parallel to the testpath.

According to an embodiment of the invention many pairs of synchronizedcomponents groups are connected by multiple operational paths. Each ofthese operational paths can be associated with one or more test pathsthat are characterized by delay differences that differ from each other.The delay differences of test path associated with different operationalpaths also differ from test path to test path.

For example, assuming that negative slacks of ΔT₁, ΔT₂ . . . ΔT_(J)should be evaluated for each operational path. According to anembodiment of the invention J test pats are defined for each operationalpaths. These J test paths can be connected in parallel to each other,thus up to J timing iterations can be required for determining theallowable timing corrections.

If, on the other hand there are Q different operational paths aredefined between synchronized components that belong to a certain pair ofsynchronized components groups then the J different test paths can bedistributed among the Q different operational paths. Thus, less then Jdifferent iterations can be required for determining the allowabletiming corrections.

For example, multiple operational paths exist between synchronizedcomponents group 281 and between synchronized components group 284. Eachoperational path can be associated with one or more test paths. Each ofthose test paths can be designed so that to provide a different delaydifference. TABLE 1 illustrates various operational paths and the timingdifferences associated with their test paths. It is assumed that sixdifferent delay differences are tested (J=6).

TABLE 1 Synchronized components included within an operational pathbetween synchronized components 2811 and Test Delay 2846 path difference2812, 2813, 2845 TP₁ ΔT₁ 2812, 2813, 2845 TP₂ ΔT₂ 2812, 2813, 2821,2822, 2823, 2824, TP₃ ΔT₃ 2825, 2841, 2842, 2843 2812, 2813, 2821, 2822,2823, 2824, TP₄ ΔT₄ 2825, 2844, 2845 2812, 2814, 2822, 2823, 2824, 2844,TP₅ ΔT₅ 2845 2812, 2814, 2822, 2823, 2824, 2844, TP₆ ΔT₆ 2845

It is noted that the delay differences are defined between a test pathand an associated operational path. As up to two test paths areassociated with a single operational path TABLE 1 illustrates a scenarioin which two iterations are required to determine the allowable timingcorrections.

It is noted that the result of timing tests of multiple test pathsprovides a set of required timing adjustments as well as timing margins.The resolution of these constraints leads to a selection of the variabledelay components that shall belong to the first set of variable delaycomponents and also determines the delay values of these selectedvariable delay components.

FIG. 7 is a flow chart of method 100 for reducing clock skews accordingto an embodiment of the invention.

Method 100 starts by stage 110 of providing a clock tree that includes aset of variable delay components. This clock tree can includes portionssuch as portion 211 of FIG. 3.

Stage 110 is followed by stage 130 of selecting a first set of variabledelay components out of multiple variable delay components to be set toa delay value other than their corresponding delay values. Referring tothe example set forth in previous FIGS. stage 130 includes selecting thevariable delay components that will form the first set of variable delaycomponents 240.

According to an embodiment of the invention stage 130 can include stage132 of determining timing violations occurring due clock skews.

According to an embodiment of the invention stage 130 can be defined asselecting 130 a first set of variable delay components out of multiplevariable delay components to be set to a delay value other than theircorresponding delay values, in view of timing violations occurring dueclock skews.

Conveniently, stage 132 is followed by stage 134 of determining timingmargins associated with multiple clock paths within the clock tree.

Stage 134 conveniently includes testing one or more test paths, whereasa delay of a test path is shorter than a delay of an operational pathassociated with the test path.

Conveniently, the testing includes performing static timing analysis ofthe operational paths.

Stage 130 is followed by stages 140 and 150. Stage 140 includes settingdelay values of variable delay components that form a first set ofvariable delay components by programming fuses.

Conveniently, stage 140 of setting includes stages 144 and 146. Stage144 includes configuring a first set of fuses to indicate an identity ofthe certain variable delay component. Referring to the example set forthin FIG. 4, this stage can include programming the first set of fuses 230to indicate the identity of each selected variable delay component.Stage 146 includes configuring a second set of fuses to indicate a delayvalue of the certain variable delay component.

Stage 150 includes setting delay values of variable delay componentsthat form a second set of variable delay components to at least onedefault value. Conveniently, the first set is smaller than one half ofthe second set.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

1. A method for reducing clock skews, the method comprises: providing aclock tree including a plurality of variable delay components, eachbranch of the clock tree including a single variable delay component;and setting a corresponding delay value of each variable delay componentincluded at a first set of the variable delay components comprisingsetting a delay value of a first variable delay component by configuringa first set of fuses to indicate an identity of the first variable delaycomponent, and by configuring a second set of fuses to indicate a delayvalue of the first variable delay component, and setting a correspondingdelay value of each variable delay component included at a second set ofthe variable delay components to at least one default value, wherein anumber of variable delay components included at the first set is lessthan one half of a number of variable delay components included at thesecond set.
 2. The method according to claim 1 wherein the setting ispreceded by selecting the first set of variable delay components.
 3. Themethod according to claim 2 wherein the selecting comprises determiningtiming violations occurring due to clock skews.
 4. The method accordingto claim 2 wherein the selecting comprises determining timing marginsassociated with multiple clock paths within the clock tree.
 5. Themethod according to claim 4 wherein the determining of timing marginscomprises testing test paths, whereas a delay of a test path is shorterthan a delay of an operational path associated with the test path. 6.The method according to claim 5 wherein the testing comprises performingstatic timing analysis of the test paths.
 7. A method for reducing clockskews, the method comprises: providing a clock tree including aplurality of variable delay components, each branch of the clock treeincluding a single variable delay component; selecting a first set ofvariable delay components of the plurality of variable delay componentsin view of timing violations occurring due to clock skews; setting acorresponding delay value of each variable delay component included atthe first set comprising setting a delay value of a first variable delaycomponent by configuring a first set of fuses to indicate an identitythe first variable delay component, and by configuring a second set offuses to indicate a delay value of the first variable delay component;and setting a corresponding delay value of each variable delay componentincluded at a second set of variable delay components of the pluralityof variable delay components to at least one default value.
 8. Themethod according to claim 7 wherein selecting comprises determiningtiming violations occurring due to clock skews.
 9. The method accordingto claim 7 wherein selecting comprises determining timing marginsassociated with multiple clock paths within the clock tree.
 10. Themethod according to claim 9 wherein determining timing margins comprisestesting test paths, and wherein a delay of a test path is shorter than adelay of an operational path associated with the test path.
 11. Themethod according to claim 10 wherein testing comprises performing statictiming analysis of the test paths.
 12. The method according to claim 7wherein providing comprises providing variable delay components atlocations that define long non-common paths with edges of the clocktree.
 13. A system, comprising: a clock tree including multiple variabledelay components including a first set and a second set of variabledelay components, each branch of the clock tree including a singlevariable delay component; a first set of fuses coupled to the multiplevariable delay components to identify variable delay components includedat the first set of variable delay components; and a second set of fusescoupled to the multiple variable delay components to identify acorresponding delay value associated with each variable delay componentincluded at the first set of variable delay components, a correspondingdelay value of each variable delay component included at the second setof variable delay components being set to at least one default delayvalue.
 14. The system according to claim 13 further comprising aselection circuit coupled to the first set of fuses, wherein theselection circuit is to send each variable delay component included atthe first set of variable delay components a delay value of thatvariable delay component.
 15. The system according to claim 13 wherein anumber of variable delay components included at the first set ofvariable delay components is less than one half of a number of variabledelay components included at the second set of variable delaycomponents.
 16. The system according to claim 13 further comprisingmultiple test paths wherein a delay of a test path is shorter than adelay of an operational path associated with the test path.
 17. Thesystem according to claim 13 wherein the variable delay components thatbelong to the first set of variable delay components and to the secondset of variable delay components are located at locations that definelong non-common paths with edges of the clock tree.
 18. The systemaccording to claim 13 wherein a number of variable delay componentsincluded at the first set of variable delay components is less than onesixth of a number of variable delay components included at the secondset of variable delay.